The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor(s), to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
The speed at which memory is accessed by, for example, system-on-chip (SOC) devices (e.g. in server computers or mobile telephones) has rapidly increased in recent years. In particular, double-data-rate (DDR) memory is a type of very fast computer memory that uses clock signals in a manner that allows twice the data to be transferred in the same amount of time. As the speed of the various signals involved in accessing the DDR memory has increased, the timing associated with such signals has become more sensitive and, thus, more prone to degradation. For example, subtle changes in environmental parameters including power, voltage, and temperature can greatly affect the timing of the memory accessing signals at high-speeds. Signal degradation can lead to data corruption within the memory.
Today, the timing associated with DDR memory access is typically initialized when the SOC is first powered up. During operation, if data associated with the memory becomes corrupted over time, the process of writing data to and reading data from the memory (i.e., the memory access process) has to be stopped and the memory has to be flushed to eliminate the corrupted data. The timing associated with the memory access process has to be re-initialized before resuming normal operation. Such interruptions in normal operation are inefficient and result in the reduction of SOC bandwidth and performance.